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?2012 silicon storage technology, inc. ds25024c 10/12 not recommended for new designs www.microchip.com features ? single voltage read and write operations ? 1.65-1.95v ? serial interface architecture ? spi compatible: mode 0 and mode 3 ? high speed clock frequency ? 75 mhz ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? ultra-low power consumption: ? active read current: 2 ma (typical @ 33 mhz) ? standby current: 5 a (typical) ? flexible erase capability ? uniform 4 kbyte sectors ? uniform 32 kbyte overlay blocks ? uniform 64 kbyte overlay blocks ? fast erase and byte-program: ? chip-erase time: 35 ms (typical) ? sector-/block-erase time: 18 ms (typical) ? byte-program time: 14 s (typical) ? auto address increment (aai) programming ? decrease total chip progra mming time over byte-pro- gram operations ? end-of-write detection ? software polling the busy bit in status register ? busy status readout on so pin ? reset pin (rst#) or programmable hold pin (hold#) option ? hardware reset pin as default ? hold pin option to suspend a serial sequence without deselecting the device ? write protection (wp#) ? enables/disables the lock-down function of the status register ? software write protection ? write protection through block-protection bits in status register ? temperature range ? industrial: -40c to +85c ? packages available ? 8-lead soic (150 mils) ? 8-bump xfbga ? all devices are rohs compliant 8 mbit 1.8v spi serial flash sst25wf080 the sst25wf080 is a member of the seri al flash 25 series family and features a four-wire, spi-compatible interface that allows for a low pin-count package which occupies less board space and ulti mately lowers total system costs. sst25wf080 spi serial flash memory is manufactured with sst proprietary, high-performance cmos superflash tec hnology. the split-gate cell design and thick-oxide tunneling injector attain better relia bility and manufacturability com- pared with alternate approaches. not recommended for new designs. please contact microchip sales for more details.
?2012 silicon storage technology, inc. ds25024c 10/12 2 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs product description the sst25wf080 is a member of the serial flash 25 series family and features a four-wire, spi-com- patible interface that allows for a low pin-count package which occupies less board space and ulti- mately lowers total system costs. sst25wf080 spi serial flash memory is manufactured with sst proprietary, high-performance cmos superflash technology. the split-gate cell design and thick- oxide tunneling injector attain better reliability and manufa cturability compared with alternate approaches. the sst25wf080 significantly improves performance and reliability, while lowering power consump- tion. the device writes (program or erase) with a single power supply of 1.65-1.95v for sst25wf080. the total energy consumed is a function of the app lied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any eras e or program operation is less than alternative flash memory technologies. the sst25wf080 is offered in both an 8-lead, 150 mils soic package and an 8-bump xfbga pack- age. see figures 2 and 3 for the pin assignments.
?2012 silicon storage technology, inc. ds25024c 10/12 3 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs block diagram figure 1: functional block diagram 1203 f01.0 i/o buffers and data latches superflash memory x - decoder control logic address buffers and latches ce# y - decoder sck si so wp# rst#/hold# serial interface note: in aai mode, the so pin functions as an ry/by# pin when configured as a ready/ busy status pin. see ?end-of-write de tection? on page 15 for more information.
?2012 silicon storage technology, inc. ds25024c 10/12 4 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs pin description figure 2: pin assignment for 8-lead soic figure 3: pin assignment for 8-bump xfbga 1 2 3 4 8 7 6 5 ce# so wp# v ss v dd rst#/hold# sck si top view 1203.25wf 08-soic-p0.0 top view (balls facing down) 1328.25wf 8-xfbga p1.0 si v ss sck wp# so v dd ce# a b c d 2 1 rst#/ hold#
?2012 silicon storage technology, inc. ds25024c 10/12 5 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs table 1: pin description symbol pin name functions sck serial clock to provide the timing of the serial interface. commands, addresses, or input data are latche d on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. si serial data input to transfer commands, addresses, or data serially into the device. inputs are latched on the rising edge of the serial clock. so serial data out- put to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock. flash busy status pin in aai mode if so is configured as a hardw are ry/by# pin. see ?end-of-write detection? on page 15 for more information. ce# chip enable the device is enabled by a high to low transition on ce#. ce# must remain low for the duration of any command sequence. wp# write protect the write protect (wp#) pin is used to enable/disable bpl bit in the status register. rst#/ hold# reset to reset the operation of the device and the internal logic. the device powers on with rst# pin functionality as default. hold to temporarily stop serial communication with spi flash memory while device is selected. this is selected by an instru ction sequence; see ?reset/hold mode? on page 7. v dd power supply to provide power supply voltage: 1.65-1.95v for sst25wf080 v ss ground t1.0 25024
?2012 silicon storage technology, inc. ds25024c 10/12 6 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs memory organization the sst25wf080 superflash memory arrays are organized in uniform 4 kbyte sectors with 16 kbyte, 32 kbyte, and 64 kbyte overlay erasable blocks. device operation the sst25wf080 are accessed through the spi (serial peripheral interface) bus compatible protocol. the spi bus consist of four control lines; chip enable (ce#) is used to select the device, and data is accessed through the serial data input (si), serial data output (so), and serial clock (sck). the sst25wf080 support both mode 0 (0,0) and mode 3 (1,1) of spi bus operations. the difference between the two modes, as shown in figure 4, is the state of the sck signal when the bus master is in stand-by mode and no data is being transferred. the sck signal is low for mode 0 and sck signal is high for mode 3. for both modes, the serial data in (si) is sampled at the rising edge of the sck clock signal and the serial data output (so) is driv en after the falling edge of the sck clock signal. figure 4: spi protocol 1203 f03.0 mode 3 sck si so ce# mode 3 don't care bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high impedance msb msb
?2012 silicon storage technology, inc. ds25024c 10/12 7 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs reset/hold mode the rst#/hold# pin provides either a hardware reset or a hold pin. from power-on, the rst#/ hold# pin defaults as a hardware reset pin (rst#) . the hold mode for this pin is a user selected option where an enable-hold instruction enables the hold mode. once selected as a hold pin (hold#), the rst#/hold# pin will be configured as a hold# pin, and goes back to rst# pin only after a power-off and power-on sequence. reset if the rst#/hold# pin is used as a reset pin, rst# pin provides a hardware method for resetting the device. driving the rst# pin high puts the device in normal operating mode. the rst# pin must be driven low for a minimum of t rst time to reset the device. the so pin is in high impedance state while the device is in reset. a successful reset will reset the status register to its power-up state. see table 4 for default power-up modes. a device reset during an active program or erase operation aborts the operation and data of the targeted address range may be corrupted or lost due to the aborted erase or program operation. the device exits aai programming mode in progress and places the so pin in high impedance state. figure 5: reset timing diagram table 2: reset timing parameters symbol parameter min max units t rst 1 1. for reset while in a programming or erase mode, the reset pulse must be >5s reset pulse width 100 ns t rhz reset to high-z output 107 ns t recr reset recovery from read 100 ns t recp reset recovery from program 10 s t rece reset recovery from erase 1 ms t2.25024 1203 f04.0 ce# so si sck rst# t recr t recp t rece t rst t rhz
?2012 silicon storage technology, inc. ds25024c 10/12 8 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs hold the hold operation enables the hold pin functionality of the rst#/hold# pin. once set to hold pin mode, the rst#/hold# pin continues functioning as a hold pin until the device is powered off and then powered on. after a power-off and power-on, the pin functionality returns to a reset pin (rst#) mode. see ?enable-hold (ehld)? on page 22 for detailed timing of the hold instruction. in the hold mode, serial sequences underway with the spi flash memory are paused without resetting the clocking sequence. to activate the hold# mode, ce# must be in active low state. the hold# mode begins when the sck active low state coincides with the falling edge of the hold# signal. the hold mode ends when the rising edge of the hold# signal coincides with the sck active low state. if the falling edge of the hold# signal does not coincide with t he sck active low state, then the device enters hold mode when the sck next reaches the acti ve low state. similarly, if the rising edge of the hold# signal does not coincide with the sck active low state, then the device exits hold mode when the sck next reaches the active low state. see figure 6 for hold condition waveform. once the device enters hold mode, so will be in high-impedance state while si and sck can be v il or v ih. if ce# is driven active high during a hold condition, the device returns to standby mode. the device can then be re-initiated with the command sequences listed in table 6. as long as hold# signal is low, the memory remains in the hold condition. to resume communication with the device, hold# must be driven active high, and ce# must be driven active low. see figure 6 for hold timing. figure 6: hold condition waveform write protection sst25wf080 provide software write protection. the write protect pin (wp#) enables or disables the lock-down function of the status register. the block-protection bits (bp3, bp2, bp1, bp0, and bpl) in the status register provide write protection to the memory array and the status register. see table 5 for the block-protection description. write protect pin (wp#) the write protect (wp#) pin enables the lock-down function of the bpl bit (bit 7) in the status register. when wp# is driven low, the execution of the write-status-register (wrsr) instruction is determined by the value of the bpl bit (see table 3). when wp# is high, the lock-down function of the bpl bit is disabled. table 3: conditions to execute write-status-register (wrsr) instruction wp# bpl execute wrsr instruction l 1 not allowed l 0 allowed h x allowed t3.0 25024 active hold active hold active 1203 f05.0 sck hold#
?2012 silicon storage technology, inc. ds25024c 10/12 9 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs status register the software status register provides status on whether the flash memory array is available for any read or write operation, whether the device is write enabled, and the state of the memory write pro- tection. during an internal erase or program operation, the status register may be read only to deter- mine the completion of an operation in progress. table 4 describes the function of each bit in the software status register. busy the busy bit determines whether there is an internal erase or program operation in progress. a ?1? for the busy bit indicates the device is busy with an operation in progress. a ?0? indicates the device is ready for the next valid operation. write enable latch (wel) the write-enable-latch bit indicates the status of the internal write-enable-latch memory. if the wel bit is set to ?1?, it indicates the device is write enabled. if the bit is set to ?0 ? (reset), it indicates the device is not write enabled and does not accept any write (program/erase) commands. the write- enable-latch bit is automatically reset under the following conditions: ? device reset ? power-up ? write-disable (wrdi) instruction completion ? byte-program instruction completion ? auto address increment (aai) programming is completed or reached its highest unpro- tected memory address ? sector-erase instruction completion ? block-erase instruction completion ? chip-erase instruction completion ? write-status-register instructions table 4: software status register bit name function default at power-up read/write 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0r 2 bp0 indicate current level of bloc k write protection (see table 5) 1 r/w 3 bp1 indicate current level of bloc k write protection (see table 5) 1 r/w 4 bp2 indicate current level of bloc k write protection (see table 5) 1 r/w 5 bp3 indicate current level of bloc k write protection (see table 5) 0 r/w 6 aai auto address increment programming status 1 = aai programming mode 0 = byte-program mode 0r 7 bpl 1 = bp3, bp2, bp1 and bp0 are read-only bits 0 = bp3, bp2, bp1 and bp0 are read/writable 0r / w t4.1 25024
?2012 silicon storage technology, inc. ds25024c 10/12 10 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs auto address increment (aai) the auto address increment programming-status bit provides status on whether the device is in aai programming mode or byte-program mode. the default at power up is byte-program mode. block-protection (bp3, bp2, bp1, bp0) the block-protection (bp3, bp2, bp1, bp0) bits define the size of the memory area to be software protected against any memory write (program or erase) operation, see table 5. the write-status- register (wrsr) instruction is used to program the bp3, bp2, bp1 and bp0 bits as long as wp# is high or the block-protect-lock (bpl) bit is ?0?. ch ip-erase can only be executed if block-protection bits are all ?0?. after power-up, bp3, bp2, bp1 and bp0 are set to defaults. see table 4 for defaults at power-up. block protection lock-down (bpl) when the wp# pin is driven low (v il ), it enables the block-protection-lock-down (bpl) bit. when bpl is set to ?1?, it prevents any further alteration of the bpl, bp3, bp2, bp1, and bp0 bits. when the wp# pin is driven high (v ih ), the bpl bit has no effect and its value is ?don?t care?. after power-up, the bpl bit is reset to ?0?. table 5: software status register block protection for sst25wf080 protection level status register bit protected memory address bp3 1 1. x = don?t care (reserved), default is ?0?. bp2 2 2. default at power-up for bp2, bp1 and bp0 is ?11?. bp1 2 bp0 2 8 mbit none x 0 0 0 none 1 (upper 16th memory, blocks 30 and 31) x 0 0 1 f0000h-fffffh 2 (upper 8th memory, blocks 28 to 31) x 0 1 0 e0000h-fffffh 3 (upper quarter memory, blocks 24 to 31) x 0 1 1 c0000h-fffffh 4 (upper half memory, blocks 16 to 31) x 1 0 0 80000h-fffffh 5 (full memory, blocks 0 to 31) x 1 0 1 00000h-fffffh x110 x111 t5.1 25024
?2012 silicon storage technology, inc. ds25024c 10/12 11 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs instructions instructions are used to read, write (erase and program), and configure the sst25wf080. the instruction bus cycles are 8 bits each for commands (op code), data, and addresses. the write- enable (wren) instruction must be executed prior to byte-program, auto address increment (aai) programming, sector-erase, block-erase, write-status-register, or chip-erase instructions. the com- plete instructions are provided in table 6. all instructions are synchronized off a high-to-low transition of ce#. inputs will be accepted on the rising edge of sck starting with the most significant bit. ce# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read-id, and read-status-register instructions). any low-to-high transition on ce #, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. instruction commands (op code), addresses, and data are all input from the most significant bit (msb) first. table 6: device operation instructions for sst25wf080 instruction description op code cycle 1 1. one bus cycle is eight clock periods. address cycle(s) 2 2. address bits above the most signi ficant bit of each density can be v il or v ih . dummy cycle(s) data cycle(s) maximum frequency read read memory 0000 0011b (03h) 3 0 1 to 33 mhz high-speed read read memory at higher speed 0000 1011b (0bh) 3 1 1 to 75 mhz 4 kbyte sec- tor-erase 3 3. 4 kbyte sector-erase addresses: use a ms -a 12, remaining addresses are don?t care but must be set either at v il or v ih. erase 4 kbyte of memory array 0010 0000b (20h) 3 0 0 32 kbyte block-erase 4 4. 32 kbyte block-erase addresses: use a ms -a 15, remaining addresses are don?t care but must be set either at v il or v ih. erase 32 kbyte block of memory array 0101 0010b (52h) 3 0 0 64 kbyte block-erase 5 erase 64 kbyte block of memory array 1101 1000b (d8h) 3 0 0 chip-erase erase full memory array 0110 0000b (60h) or 1100 0111b (c7h) 000 byte-program to program one data byte 0000 0010b (02h) 3 0 1 aai-word- program 6 auto address increment programming 1010 1101b (adh) 3 0 2 to rdsr 7 read-status-register 0000 0101b (05h) 0 0 1 to ewsr 8 enable-write-status-register 0110 0000b (50h) 0 0 0 wrsr write-status-register 0000 0001b (01h) 0 0 1 wren 8 write-enable 0000 0110b (06h) 0 0 0 wrdi write-disable 0000 0100b (04h) 0 0 0 rdid 9 read-id 1001 0000b (90h) or 1010 1011b (abh) 301 to ebsy enable so to output ry/by# status during aai programming 0111 0000b (70h) 0 0 0 dbsy disable so to output ry/by# status during aai programming 1000 0000b (80h) 0 0 0 jedec-id jedec id read 1001 1111b (9fh) 0 0 3 to ehld enable hold# pin functionality of the rst#/hold# pin 1010 1010b (aah) 0 0 0 t6.0 25024
?2012 silicon storage technology, inc. ds25024c 10/12 12 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs read (33 mhz) the read instruction, 03h, supports up to 33 mhz read. the device outputs a data stream starting from the specified address location. the data stream is continuous through all addresses until termi- nated by a low-to-high transition on ce#. the internal address pointer automatically increments until the highest memory address is reached. once the highest memory address is reached, the address pointer automatically increments to the beginning (wrap-around) of the address space. for example, for 8 mbit density, once the dat a from the address location fffffh is read, the next output is from address location 000000h. the read instruction is initiated by executing an 8-bit command, 03h, fol- lowed by address bits a 23 -a 0 . ce# must remain active low for the duration of the read cycle. see fig- ure 7 for the read sequence. figure 7: read sequence 5. 64 kbyte block-erase addresses: use a ms -a 16, remaining addresses are don?t care but must be set either at v il or v ih. 6. to continue programming to the next sequential address location , enter the 8-bit command, adh, followed by 2 bytes of data to be programmed. data byte 0 will be programmed into the initial address [a 23 -a 1 ] with a 0 =0, data byte 1 will be programmed into the initial address [a 23 -a 1 ] with a 0 = 1. 7. the read-status-register is continuous with ongoing clock cycles until terminated by a low to high transition on ce#. 8. either ewsr or wren followed by wrsr will write to the status register. the ewsr-wrsr sequence provides back- ward compatibility to the sst25vf/lf series. the wren-wrsr sequence is recommended for new designs. 9. manufacturer?s id is read with a 0 =0, and device id is read with a 0 =1. all other address bits are 00h. the manufac- turer?s id and device id output stream is continuous until terminated by a low-to-high transition on ce#. 1203 f06.0 ce# so si sck add. 012345678 add. add. 03 high impedance 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out
?2012 silicon storage technology, inc. ds25024c 10/12 13 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs high-speed-read (75 mhz) the high-speed-read instruction supporting up to 75 mhz read is initiated by executing an 8-bit com- mand, 0bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce# must remain active low for the duration of the high-speed-read cycle. see figure 8 for the high-speed-read sequence. following a dummy cycle, the high-speed-read instru ction outputs the data starting from the speci- fied address location. the data output stream is continuous through all addresses until terminated by a low-to-high transition on ce#. the internal addres s pointer will automatically increment until the high- est memory address is reached. once the highes t memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space. for example, for 2 mbit density, once the data from address location 7ffffh is read, th e next output will be from address location 000000h. figure 8: high-speed-read sequence 1203 f07.0 ce# so si sck add. 012345678 add. add. 0b high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 x msb mode 0 mode 3 d out d out d out d out 80 71 72 d out msb
?2012 silicon storage technology, inc. ds25024c 10/12 14 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs byte-program the byte-program instruction programs the bits in the selected byte to the desired data. the selected byte must be in the erased state (ffh) when initiating a program operation. a byte-program instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the byte-program inst ruction. the byte-program instruction is initiated by executing an 8-bit command, 02h, followed by address bits [a 23 -a 0 ]. following the address, the data is input in order from msb (bit 7) to lsb (bit 0). ce# must be driven high before the instruction is exe- cuted. the user may poll the busy bit in the software status register or wait t bp for the completion of the internal self-timed byte-program operation. see figure 9 for the byte-program sequence. figure 9: byte-program sequence 1203 f08.0 ce# so si sck add. 012345678 add. add. d in 02 high impedance 15 16 23 24 31 32 39 msb lsb mode 3 mode 0 msb
?2012 silicon storage technology, inc. ds25024c 10/12 15 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs auto address increment (aai) word-program the aai program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. this feature decreases total programming time when multiple bytes or the entire memory array is to be programmed. an aai word program instruction pointing to a pro- tected memory area will be ignored . the selected address range must be in the erased state (ffh) when initiating an aai word program operation. while within aai word programming sequence, the only valid instructions are aai word (adh), rdsr (05h), or wrdi (04h). users have three options to determine the completion of each aai word program cycle: hardware detection by reading the serial output, software detection by po lling the busy bit in the software status register or wait t bp. refer to end-of-write detection section for details. prior to any write operation, the write-enable (w ren) instruction must be executed. the aai word program instruction is initiated by executing an 8-bit command, adh, followed by address bits [a 23 -a 0 ]. following the addresses, two bytes of data are input sequentially, each one from msb (bit 7) to lsb (bit 0). the first byte of data (d0) will be programmed into the initial address [a 23 -a 1 ] with a 0 = 0, the second byte of data (d1) will be pr ogrammed into the initial address [a 23 -a 1 ] with a 0 = 1. ce# must be driven high before the aai word program instruction is executed. the user must check the busy sta- tus before entering the next valid command. once the device indicates it is no longer busy, data for the next two sequential addresses may be programmed and so on. when the last desired byte had been entered, check the busy status using the hardware method or the rdsr instruction and execute the write-disable (wrdi) instruction, 04h, to terminate aai. check the busy status after wrdi to deter- mine if the device is ready for any command. see figures 12 and 13 for aai word programming sequence. there is no wrap mode during aai programming; once the highest unprotected memory address is reached, the device will exit aai operation and reset the write-enable-latch bit (wel = 0) and the aai bit (aai = 0). end-of-write detection there are three methods to determine completion of a program cycle during aai word programming: hardware detection by read ing the serial output, software detect ion by polling the busy bit in the soft- ware status register or wait t bp . hardware end-of-write detection the hardware end-of-write detection method eliminates the overhead of polling the busy bit in the software status register during an aai word program operation. the 8-bit command, 70h, configures the serial output (so) pin to indicate flash busy status during aai word programming, as shown in figure 10. the 8-bit command, 70h, must be executed prior to executing an aai word-program instruction. once an inte rnal programming operati on begins, asserting ce# will immediately drive the status of the internal flash status on the so pin. a ?0? indicates the device is busy and a ?1? indicates the device is ready for the next instruction. de-asserting ce# will return the so pin to tri-state. the 8-bit command, 80h, disables the serial output (so) pin to output busy status during aai-word- program operation, and re-configures so as an output pin. in this st ate, the so pin will function as a normal serial output pin. at this time, the rdsr command can poll the status of the software status register. this is shown in figure 11.
?2012 silicon storage technology, inc. ds25024c 10/12 16 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs figure 10: enable so as hardware ry/by# during aai programming figure 11: disable so as hardware ry/ by# during aai programming figure 12: auto address increment (aai) word program sequence with hardware end-of-write detection ce# so si sck 01234567 70 high impedance mode 0 mode 3 1203 f09.0 msb ce# so si sck 01234567 80 high impedance mode 0 mode 3 1203 f10.0 msb ce# si sck so d out 1203 f11.0 last 2 data bytes wdri to exit aai mode wait t bp or poll software status register to load any command check for flash busy status to load next valid 1 command load aai command, address, 2 bytes data note: 1. valid commands during aai programming: aai command or wrdi command 2. user must configure the so pin to output flash busy status during aai programming 078 32 47 15 16 23 24 31 0 4039 7 8 15 16 23 7 8 15 16 23 70 15 78 00 aaa ad d0 ad mode 3 mode 0 d1 d2 d3 ad d n-1 d n wrdi rdsr
?2012 silicon storage technology, inc. ds25024c 10/12 17 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs figure 13: auto address increment (aai) word program sequence with software end-of-write detection 078 32 47 15 16 23 24 31 0 4039 7 8 15 16 23 7 8 15 16 23 70 15 78 00 ce# si sck so d out mode 3 mode 0 1203 f12.0 wait t bp or poll software status register to load any command note: 1. valid commands during aai programming: aai command or wrdi command wait t bp or poll software status register to load next valid 1 command last 2 data bytes wdri to exit aai mode load aai command, address, 2 bytes data aaa ad d0 ad d1 d2 d3 ad d n-1 d n wrdi rdsr
?2012 silicon storage technology, inc. ds25024c 10/12 18 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs sector-erase the sector-erase instruction clears all bits in the selected 4 kbyte sector to ffh. a sector-erase instruction applied to a pr otected memory area will be ignored. pr ior to any write operation, the write- enable (wren) instruction must be executed. ce# must remain active low for the duration of any com- mand sequence. the sector-erase instruction is initiated by executing an 8-bit command, 20h, fol- lowed by address bits [a 23 -a 0 ]. address bits [a ms -a 12 ] (a ms = most significant address) are used to determine the sector address (sa x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t se for the completion of the internal self-timed sector-erase cycle. see figure 14 for the sector- erase sequence. figure 14: sector-erase sequence 32-kbyte block-erase the block-erase instruction clears all bits in the selected 32 kbyte block to ffh. a block-erase instruction applied to a protected memory area is ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the block-erase instruction is initiated by executing an 8-bit command, 52h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 15 ] (a ms = most significant address) are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruc- tion is executed. poll the busy bit in the software status register or wait t be for the completion of the inter- nal self-timed block-erase. see figure 15 for the block-erase sequences. figure 15: 32-kbyte block-erase sequence ce# so si sck add. 012345678 add. add. 20 high impedance 15 16 23 24 31 mode 0 mode 3 1203 f13.0 msb msb ce# so si sck addr 012345678 addr addr 52 high impedance 15 16 23 24 31 mode 0 mode 3 1203 f14.0 msb msb
?2012 silicon storage technology, inc. ds25024c 10/12 19 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs 64-kbyte block-erase the block-erase instruction clears all bits in the selected 64 kbyte block to ffh. a block-erase instruction applied to a protected memory area is ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the block-erase instruction is initiated by executing an 8-bit command, d8h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 16 ] (a ms = most significant address) are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruc- tion is executed. poll the busy bit in the software status register or wait t be for the completion of the inter- nal self-timed block-erase. see figure 16 for the block-erase sequences. figure 16: 64-kbyte block-erase sequence chip-erase the chip-erase instruction clears a ll bits in the device to ffh. a ch ip-erase instruct ion is ignored if any of the memory area is protected. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the dura tion of the chip-erase instruction sequence. the chip-erase instruction is initiated by executing an 8-bit command , 60h or c7h. ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t ce for the completion of the intern al self-timed chip-erase cycle. see figure 17 for the chip-erase sequence. figure 17: chip-erase sequence ce# so si sck addr 012345678 addr addr d8 high impedance 15 16 23 24 31 mode 0 mode 3 1203 f15.0 msb msb ce# so si sck 01234567 60 or c7 high impedance mode 0 mode 3 1203 f16.0 msb
?2012 silicon storage technology, inc. ds25024c 10/12 20 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs read-status-register (rdsr) the read-status-register (rdsr) instruction, 05h, allows reading of the status register. the status register may be read at any time even during a write (program/erase) operation. when a write opera- tion is in progress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce# must be driven low before the rdsr instruc- tion is entered and remain low unt il the status data is read. read-status-register is continuous with ongoing clock cycles until it is term inated by a low to high transition of the ce#. see figure 18 for the rdsr instruction sequence. figure 18: read-status-register (rdsr) sequence write-enable (wren) the write-enable (wren) instruction, 06h, sets the write-enable-latch bit in the status register to 1 allowing write operations to occur. the wren instruction must be executed prior to any write (pro- gram/erase) operation. the wren instruction may also be used to allow execution of the write-sta- tus-register (wrsr) instruction; however, the wr ite-enable-latch bit in the status register will be cleared upon the rising edge ce# of the wrsr instruction. ce# must be driven high before the wren instruction is executed. see figure 19 for the wren instruction sequence. figure 19: write enable (wren) sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1203 f17.0 mode 3 sck si so ce# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 mode 0 high impedance status register out msb msb ce# so si sck 01234567 06 high impedance mode 0 mode 3 1203 f18.0 msb
?2012 silicon storage technology, inc. ds25024c 10/12 21 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs write-disable (wrdi) the write-disable (wrdi) instruction, 04h, resets the write-enable-latch bit and aai to 0 disabling any new write operations from occurring. the wrdi instruction will not terminate any programming operation in progress. any program operation in progress may continue up to t bp after executing the wrdi instruction. ce# must be driven high before the wrdi instruction is ex ecuted. see figure 20 for the wrdi instruction sequence. figure 20: write disable (wrdi) sequence enable-write-status-register (ewsr) the enable-write-status-register (ewsr) instruction arms the write-status-register (wrsr) instruction and opens the status register for alteration. the write-status-register instruction must be executed immediately after the execution of the enable-write-status-register instruction. this two- step instruction sequence of the ewsr instruction followed by the wrsr instruction works like sdp (software data protection) command structure which prevents any accidental alteration of the status register values. ce# must be driven low before the ewsr instruction is entered and must be driven high before the ewsr instruction is executed. see figure 21 for ewsr instruction followed by wrsr instruction. ce# so si sck 01234567 04 high impedance mode 0 mode 3 1203 f19.0 msb
?2012 silicon storage technology, inc. ds25024c 10/12 22 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs write-status-register (wrsr) the write-status-register instruction writes new values to the bp3, bp2, bp1, bp0, and bpl bits of the status register. ce# must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wrsr instruction is executed. see figure 21 for ewsr or wren and wrsr instruction sequences. executing the write-status-register instruction will be ignored when wp# is low and bpl bit is set to ?1?. when the wp# is low, the bpl bit can only be set from ?0? to ?1? to lock-down the status register, but cannot be reset from ?1? to ?0?. when wp# is high, the lock-down function of the bpl bit is disabled and the bpl, bp0, bp1, bp2, and bp3 bits in the status register can all be changed. as long as bpl bit is set to ?0? or wp# pin is driven high (v ih ) prior to the low-to-high transition of the ce# pin at the end of the wrsr instruction, the bits in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as altering the bp0, bp1, bp2, and bp3 bits at the same time. see table 3 for a summary description of wp# and bpl functions. figure 21: enable-write-status-register (ewsr) or write-enable (wren) and write-sta- tus-register (wrsr) sequence enable-hold (ehld) the 8-bit command, aah, enable-hold instruction enables the hold functionality of the rst#/ hold# pin. ce# must remain active low for the duration of the enable-hold instruction sequence. ce# must be driven high before the instruction is executed. see figure 22 for the enable-hold instruction sequence. figure 22: enable-hold sequence 1203 f20.0 mode 3 high impedance mode 0 status register in 76543210 msb msb msb 01 mode 3 sck si so ce# mode 0 50 or 06 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ce# so si sck 01234567 aa high impedance mode 0 mode 3 1203 f21.0 msb
?2012 silicon storage technology, inc. ds25024c 10/12 23 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs read-id the read-id instruction identifies the manufacturer as sst and the device as sst25wf080. use the read-id instruction to identify sst device when us ing multiple manufacturers in the same socket. see ta bl e 7 . the device information is read by executing an 8-bit command, 90h or abh, followed by address bits [a 23 -a 0 ]. following the read-id instruction, the manufacturer?s id is located in address 000000h and the device id is located in address 000001h. once the device is in read-id mode, the manufacturer?s and device id output data toggles between address 000000h and 000001h until terminated by a low to high transition on ce#. figure 23: read-id sequence table 7: product identification address data manufacturer?s id 000000h bfh device id sst25wf080 000001h 05h t7.25024 1203 f22.0 ce# so si sck 00 012345678 00 add 90 or ab high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 bf device id bf device id note: 1. the manufacturer's and device id output stream is continuous until terminated by a low to high transition on ce#. 2. 00h will output the manfacturer's id first and 01h will output device id first before toggling between the two. high impedance mode 3 mode 0 msb msb msb
?2012 silicon storage technology, inc. ds25024c 10/12 24 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs jedec read-id the jedec read-id instruction identifies the device as sst25wf080 and the manufacturer as sst. the device information can be read from executing the 8-bit command, 9fh. following the jedec read-id instruction, the 8-bit manufacturer?s id, bfh, is output from the device. after that, a 16-bit device id is shifted out on the so pin. the device id is assigned by the manufacturer and contains the type of memory in the first byte and the memory ca pacity of the device in the second byte. see figure 24 for the instruction sequence. the jedec read id instruction is terminated by a low to high transi- tion on ce# at any time during data output. figure 24: jedec read-id sequence table 8: jedec read-id data-out device id manufacturer?s id (byte 1) memory type (byte 2) memory capacity (byte 3) bfh 25h 05h t8.0 25024 25 05h 1203 f23.0 ce# so si sck 012345678 high impedance 15 1614 28 29 30 31 bf mode 3 mode 0 msb msb 9 10111213 1718 32 34 9f 19 20 21 22 23 33 24 25 26 27
?2012 silicon storage technology, inc. ds25024c 10/12 25 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs electrical specifications absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating con- ditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +12 5c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to + 150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. output shorted for no more than one second. no more than one output shorted at a time. table 9: operating range range ambient temp v dd industrial -40c to +85c 1.65-1.95v t9.1 25024 table 10: ac conditions of test input rise/fall time output load 5ns c l = 30 pf t10.1 25024
?2012 silicon storage technology, inc. ds25024c 10/12 26 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs power-up specifications all functionalities and dc specif ications are specified for a v dd ramp rate of greater than 1v per 100 ms (0v to 1.8v in less than 180 ms). if the vdd ramp rate is slower than 1v/100 ms, a hardware reset is required. the recommended v dd power-up to reset# high time should be greater than 100 s to ensure a proper reset. see table 11 and figures 25 and 26 for more information. figure 25: power-up reset diagram figure 26: power-up timing diagram table 11: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for initial qualification and after a design or process change that could affect this paramet er. v dd min to read operation 100 s t pu-write 1 v dd min to write operation 100 s t11.0 25024 1203 f37.0 v dd reset# ce# t pu-read v dd min 0v v ih t recr note: see table 2 on page 7 for t recr parameter. time v dd min v dd max v dd device fully accessible t pu-read t pu-write chip selection is not allowed. commands may not be accepted or properly interpreted by the device. 1203 f27.0
?2012 silicon storage technology, inc. ds25024c 10/12 27 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs dc characteristics table 12: dc operating characteristics symbol parameter limits test conditions min typ 1 1. value characterized, not fully tested in production. max units i ddr read current 2 5 ma ce#=0.1 v dd /0.9 v dd @33 mhz, so=open i ddr2 read current 4 9 ma ce#=0.1 v dd /0.9v dd @75 mhz, so=open i ddw program and erase current 6 10 ma ce#=v dd i sb standby current 5 20 a ce#=v dd , v in =v dd or v ss i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.3 v v dd =v dd min v ih input high voltage 0.7 v dd vv dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t12.0 25024 table 13: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. output pin capacitance v out = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t13.0 25024 table 14: reliability characteristics symbol parameter minimum sp ecification units test method n end 1 1. this parameter is measured only for initial qualification and after a desig n or process change that could affect this parameter. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t14.0 25024
?2012 silicon storage technology, inc. ds25024c 10/12 28 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs ac characteristics table 15: ac operating characteristics limits - 33 mhz limits - 75 mhz symbol parameter min max min max units f clk 1 1. maximum clock frequency for read instruction, 03h, is 33 mhz serial clock frequency 33 75 mhz t sckh serial clock high time 13 6 ns t sckl serial clock low time 13 6 ns t sckr serial clock rise time 0.1 0.1 v/ns t sckf serial clock fall time 0.1 0.1 v/ns t ces 2 2. relative to sck ce# active setup time 12 5 ns t ceh 2 ce# active hold time 12 5 ns t chs 2 ce# not active setup time 10 5 ns t chh 2 ce# not active hold time 10 5 ns t cph ce# high time 50 25 ns t chz ce# high to high-z output 20 7 ns t clz sck low to low-z output 0 0 ns t ds data in setup time 5 2 ns t dh data in hold time 5 4 ns t hls hold# low setup time 10 6 ns t hhs hold# high setup time 10 6 ns t hlh hold# low hold time 15 6 ns t hhh hold# high hold time 10 6 ns t hz hold# low to high-z output 20 7 ns t lz hold# high to low-z output 20 7 ns t oh output hold from sck change 0 0 ns t v output valid from sck 12 6 ns t se sector-erase 30 30 ms t be block-erase 30 30 ms t sce chip-erase 60 60 ms t bp 3 3. aai-word program t bp maximum specification is also at 25 s maximum time byte-program 25 25 s t15.2 25024
?2012 silicon storage technology, inc. ds25024c 10/12 29 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs figure 27: serial input timing diagram figure 28: serial output timing diagram high-z high-z ce# so si sck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 1203 f24.0 1203 f25.0 ce# si so sck msb t clz t v t sckh t chz t oh t sckl lsb
?2012 silicon storage technology, inc. ds25024c 10/12 30 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs figure 29: hold timing diagram figure 30: ac input/output reference waveforms t hz t lz t hhh t hls t hlh t hhs 1203 f26.0 hold# ce# sck so si 1203 f28.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic ?1? and v ilt (0.1v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v ht (0.6v dd ) and v lt (0.4v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test
?2012 silicon storage technology, inc. ds25024c 10/12 31 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs product ordering information valid combinations for sst25wf080 sst25wf080-75-4i-saf sst25wf080-75-4i-zae note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid co mbinations and to determine availability of new combi- nations. sst25 wf080 -75 -4i -sae xx x x xxx -xx -xx - xxx environmental attribute e 1 = non-pb f 2 = non-pb / non-sn contact (lead) finish: nickel plating with gold top (outer) layer package modifier a = 8 leads package type z = xfbga s = soic 150 mil body width temperature range i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles operating frequency 75 = 75 mhz device density 080 = 8 mbit voltage w= 1.65-1.95v product series 25 = serial peripheral interface flash memory 1. environmental suffix ?e? denotes non-pb solder. sst non-pb solder devices are ?rohs compliant?. 2. environmental suffix ?f? denotes non-pb/non-sn sol- der. sst non-pb/non-sn sol der devices are ?rohs compliant?.
?2012 silicon storage technology, inc. ds25024c 10/12 32 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs packaging diagrams figure 31: 8-lead small outline integrated ci rcuit (soic) 150 mil body width sst package code: sa note: for more information about the za package, including a copy of the package diagram, please contact your sst representative. 08-soic-5x6-sa-8 n ote: 1. complies with jedec pub lication 95 ms-012 aa dimensions, altho u gh some dimensions may b e more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maxim um allo w ab le mold flash is 0.15 mm at the package ends and 0.25 mm betw een leads. top view side view end view 5.0 4.8 6.20 5.80 4.00 3.80 pin #1 identifier 0.51 0.33 1.27 bsc 0.25 0.10 1.75 1.35 7 4 places 0.25 0.19 1.27 0.40 45 7 4 places 0 8 1mm
?2012 silicon storage technology, inc. ds25024c 10/12 33 8 mbit 1.8v spi serial flash sst25wf080 not recommended for new designs table 16: revision history number description date 00 ? initial release of data sheet sep 2007 01 ? revised active read current, standby current, chip-erase time, and sector-/block-erase time in features on page 1 ? added a footnote to table 2 reset timing parameters ? revised table 6 on page 11 ? revised table 12 on page 27 ? revised table 15 on page 28 ? revised figure 12 and figure 13 ? revised product ordering information and valid combinations ? revised t hls , t hhs , t hlh , and t hhh in table 15 on page 28 from 5 ns to 6ns. apr 2009 02 ? changed standby current: from 5 ma to 5 a in features on page 1 ? added the z1a package may 2009 03 ? removed z1ae package information ? added zae package information ? updated sst address information on page 29 apr 2010 a ? updated document status to ?data sheet? ? applied new document format ? updated spec number from s71203 to ds25024 aug 2011 b ? fixed incorrect voltage in table 9 on page 25 mar 2012 c ? updated the caption for figure 31 to reflect the correct package width oct 2012 ? 2012 silicon storage technology, inc?a microchi p technology company. all rights reserved. sst, silicon storage technology, the sst l ogo, superflash, mtp, and flashflex are regi stered trademarks of silicon storage tech - nology, inc. mpf, sqi, serial quad i/o, and z-scale are trad emarks of silicon storage technology, inc. all other trademarks and registered trademarks mentioned herein are the property of their respective owners. specifications are subject to change without notice. refer to www.microchip.com for th e most recent documentation. for the most current package drawings, please see the packaging specific ation located at http://www.microchip.com/packaging. memory sizes denote raw storage capacity ; actual usable capacity may be less. sst makes no warranty for the use of its products other than those ex pressly contained in the standar d terms and conditions of sale. for sales office locations and information, please see www.microchip.com. silicon storage technology, inc. a microchip technology company www.microchip.com isbn:978-1-62076-628-6

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